Jean-luc Dekeyser, PR (CE1)
Team-Project DaRT - LIFL
Office 1 Address:
LIFL, Cité scientifique
59655 Villeneuve d'Ascq, France
Telephone : +33 (0)
Fax : +33 (0) 3 20 43 65 66
Mail : jean-luc[dot]dekeyser[at]lifl[dot]fr
I am professor in computer
science at Université des
Sciences et Technologies de Lille (USTL), France.
My research activities are done at Laboratoire d’Informatique
Fondamentale de Lille. I am also member of INRIA Lille
- Nord Europe Dreampal project.
My research activities focus on modelling, design and
management of dynamically massivelly parallel
reconfigurable systems. More precisely I investigate the
- MARTE extensions for reconfigurable systems
- Distributed reconfiguration control,
- Reflexive softcore processors, the Homade processor.
- Massivelly parallel reflexive processor,
I am developping the Homade
processor is an open-source VHDL code for FPGA. Last
version is running on vilinx Spartan 3E. On going wors
concern Virtex 7 platforms.
The Homade processor has the following characteristics.
- Ultra RISC processor with 12 different instrcutions
- Stack processor with ZERO address style
- A "All is IP" oriented hardware. A partiicular
instruction IP allows to link ( static or dynamic way)
any IP instance and to trig this IP during a
- Homade is reflexive with iineercession facility. An
Virtual Component can be dynamically associated to a
hardcore developped in vhdl or to a softcore
developped in Homade function. Switching is achieved
by a particular native instrction WIM.
- Homade is a 3 stage Pipeline processor
- Homade supported multi SPMD execution model by
- Homade is used for teaching with the Nexys 3 board
with 100 master'students
French documentations for students are available on the Homade_web_site