Pierre Boulet's Papers

[1]

Abou El Hassan Benyamina and Pierre Boulet. An hybrid algorithm for mapping on noc architectures. In 2nd International Conference on Metaheuristics and Nature Inspired Computing, META’08, Hammamet, Tunisia, October 2008.

[2]

Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet, and Jean-Luc Dekeyser. Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP Journal on Embedded Systems, 2008. (To appear).

[3]

Calin Glitia and Pierre Boulet. High Level Loop Transformations for Multidimensional Signal Processing Embedded Applications. In International Symposium on Systems, Architectures, MOdeling, and Simulation (SAMOS VIII), Samos, Greece, July 2008.

Array-OL specification model is a mixed graphical-textual language designed to model multidimensional intensive signal processing applications. Data and task parallelism are specified directly in the model. High level transformations are defined on this model, allowing the refactoring of an application and furthermore providing directions for optimization. The resemblances between with the wide-known and used Loop transformations lead us to try taking concepts and results from this domain and see how they fit in Array-OL context.

[4]

Jean-Luc Dekeyser, Abdoulaye Gamatié, Anne Etien, Rabie Ben Atitallah, and Pierre Boulet. Using the UML Profile for MARTE to MPSoC Co-Design. In First International Conference on Embedded Systems & Critical Applications (ICESCA'08), Tunis, Tunisia, May 2008.

The increasing amount of hardware resources in next generation MultiProcessor Systems-on-Chip (MPSoC) calls for efficient design methodologies and tools to reduce their development complexity. This paper presents a candidate MPSoC design environment Gaspard2, which uses the MARTE (Modeling and Analysis of Real-Time and Embedded systems) standard profile for high-level system specification. Gaspard2 adopts a methodology based on Model- Driven Engineering. It promotes separation of concerns, reusability and automatic model refinement from higher abstraction levels to executable descriptions.

[5]

Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, and Jean-Luc Dekeyser. Using An MDE Approach for Modeling of Interconnection networks. In The International Symposium on Parallel Architectures, Algorithms and Networks Conference (ISPAN 08), Sydney, Australia, May 2008.

Modern System-on-Chip (SoCs) are becoming more complex with the integration of heterogeneous components. Therefore, a high performance interconnection medium is required to handle the complexity. Thus Network-on-Chips (NoCs) come into play enabling the integration of more Intellectual Properties (IPs) into the SoC with increased performance. The NoCs are based on the concept of Interconnection Networks for connecting parallel machines. In the recent MARTE (Modeling and Analysis of Real-time and Embedded Systems) Profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topologies. This paper presents a modeling methodology based on that notation that can be used to model the Delta Network family of Interconnection Networks for NoC construction.

[6]

Éric Piel, Rabie Ben Atitallah, Philippe Marquet, Samy Meftali, Smaïl Niar, Anne Etien, Jean-Luc Dekeyser, and Pierre Boulet. Gaspard2: from marte to systemc simulation. In Proceeedings of the DATE'08 workshop on Modeling and Analyzis of Real-Time and Embedded Systems with the MARTE UML profile, March 2008.

[7]

Pierre Boulet. Formal semantics of Array-OL, a domain specific language for intensive multidimensional signal processing. Research Report RR-6467, INRIA, March 2008.

[8]

Abou El Hassan Benyamina and Pierre Boulet. Multi-objective mapping for noc architecture. Journal of Digital Information Management, 5(6):378–384, December 2007.

[9]

Souha Kamoun and Pierre Boulet. Une approche modèle pour la génération de scénarios de tests : Application au système ERTMS/ETCS. In Workshop International : Logistique and Transport 2007, Sousse, Tunisie, November 2007.

[10]

Souha Kamoun and Pierre Boulet. Model-Based Testing of the ERTMS System with SysML and MARTE. In MoDeVVa'07, Nashville, USA, October 2007.

[11]

Pierre Boulet, Philippe Marquet, Éric Piel, and Julien Taillard. Repetitive Allocation Modeling with MARTE. In Forum on specification and design languages (FDL'07), Barcelona, Spain, September 2007. Invited paper, Author names alphabetically ordered.

With the advent of multi-processor Systems-on-Chip (MpSoC), the need for modeling the distribution of a parallel application onto a parallel hardware architecture is increasing. The recent standard profile for the modeling and analysis of real-time and embedded systems (MARTE) provides a notation for the modeling of regular distributions. This notation allows to distribute computations to processing elements, data to shared or distributed memories, etc. In this paper we will highlight the expressivity of this notation and clarify its usage through examples and comparisons to other distribution notations such as in High Performance Fortran.

[12]

Rabie Ben Atitallah, Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Antoine Honoré, Ouassila Labbani, Sébastien Le Beux, Philippe Marquet, Éric Piel, Julien Taillard, and Huafeng Yu. Gaspard2 UML profile documentation. Technical Report 0342, INRIA, September 2007.

This document describes the current UML profile of Gaspard2. This profile extends the UML semantics to allow the user to describe a SoC (System-on-Chip) in three steps: the application (behavior of the Soc), the hardware architecture, and the association of the application to the hardware architecture. The application is represented following a data flow model, but additional mechanisms permit the usage of control flow on those applications. In addition to those notions, the profile contains a package introducing factorization mechanisms to enable the compact description of massively parallel and repetitive systems.

Ce document décrit le profil UML Gaspard2 actuel. Ce profil étend la sémantique d'UML pour permettre à l'utilisateur de décrire un SoC (système-sur-puce) en trois étapes : l'application (le comportement du SoC), l'architecture matérielle, et l'association de l'application sur l'architecture. L'application est représentée selon un modèle de flux de données, mais des mécanismes supplémentaires permettent l'usage d'un flux de contrôle sur ces applications. En complément à ces notions, le profil contient un paquetage introduisant des mécanismes de factorisation rendant possible la description compacte de systèmes massivement parallèles répétitifs.

[13]

Imran Rafiq Quadri, Pierre Boulet, and Jean-Luc Dekeyser. Modeling of topologies of interconnection networks based on multidimensional multiplicity. Research Report RR-6201, INRIA, May 2007.

Modern SoCs are becoming more complex with the integration of heterogeneous components (IPs). For this purpose, a high performance interconnection medium is required to handle the complexity. Hence NoCs come into play enabling the integration of more IPs into the SoC with increased performance. These NoCs are based on the concept of Interconnection networks used to connect parallel machines. In response to the MARTE RFP of the OMG, a notation of multidimensional multiplicity has been proposed which permits to model repetitive structures and topologies. This report presents a modeling methodology based on this notation that can be used to model a family of Interconnection Networks called Delta Networks which in turn can be used for the construction of NoCs.

[14]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'06, chapter UML2 Profile for Modeling Controlled Data Parallel Applications. ChDL. Springer, 2007. (To appear).

[15]

Abou El Hassan Benyamina and Pierre Boulet. Multi-objective mapping for NoC architectures. In 1st International Conference on Digital Communications and Computer Applications, pages 132–139, Jordan, March 2007.

[16]

Pierre Boulet. Array-OL revisited, multidimensional intensive signal processing specification. Research Report RR-6113, INRIA, February 2007.

[17]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet, and Jean-Luc Dekeyser. Synchronous modeling of data-intensive applications. In International Open Workshop on Synchronous Programming (Synchron 2006), Alpe d'Huez, France, November 2006.

[18]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet, and Jean-Luc Dekeyser. Vers des transformations d'applications à parallélisme de données en équations synchrones. In 9e édition de SYMPosium en Architectures nouvelles de machines (SympA'2006), Perpignan, France, October 2006.

Ce papier présente les premiers résultats d'une étude concernant la transformation d'applications à parallélisme de données en équations synchrones. Les applications considérées sont exprimées à l'aide du métamodèle GASPARD qui étend le langage ARRAY-OL, dédié aux applications de traitement de données intensives. Le principe général des transformations envisagées est exposé ainsi que les idées de mise en oeuvre. Les modèles synchrones résultants permettent d'aborder plusieurs questions liées à la validation formelle, par exemple, vérification de propriétés de synchronisabilité, de latence, etc, en utilisant les outils et techniques formels offerts par la technologie synchrone. Ils permettent ainsi l'accès à des fonctionnalités complémentaires avec celles de l'environnement associé à GASPARD, qui propose uneméthodologie de conception conjointe matériel/logiciel de systèmes intégrés sur puce. Les transformations suivront une approche d'Ingénierie dirigée par les modèles (IDM/MDE). Des perspectives sont mentionnées concernant l'introduction d'automates de contrôle au sein des modèles obtenus.

[19]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. UML2 profile for modeling controlled data parallel applications. In Forum on specification and Design Languages (FDL'06), Darmstadt, Germany, September 2006.

[20]

Pierre Boulet, Cédric Dumoulin, and Antoine Honoré. From MDD concepts to experiments and illustrations, chapter Model Driven Engineering for System-on-Chip Design. ISTE, Hermes science and Lavoisier, September 2006.

[21]

Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet, and Jean-Luc Dekeyser. Synchronous modeling of data intensive applications. Research Report 5876, INRIA, April 2006.

In this report, we present the first results of a study on the modeling of data-intensive parallel applications following the synchronous approach. More precisely, we consider the Gaspardextension of Array-Ol, which is dedicated to System-on-Chip codesign. We define an associated synchronous dataflow equational model that enables to address several design correctness issues (e.g. verification of frequency / latency constraints) using the formal tools and techniques provided by the synchronous technology. We particularly illustrate a synchronizability analysis using affine clock systems. Directions are drawn from these bases towards modeling hierarchical applications, and adding control automata involving verification.

Dans ce rapport, nous présentons les premiers résultats d'une étude sur la modélisation d'applications parallèles de traitement de données intensives, basée sur l'approche synchrone. Plus exactement, nous considérons l'extension Gaspard d'Array-Ol, qui est dédiée à la conception conjointe de systèmes intégrés sur puce. Nous définissons un modèle flot de données synchrone équationnel associé, qui permet d'aborder plusieurs questions liées à la correction lors de la conception (par exemple, vérification de contraintes de latence ou de fréquence), en utilisant les outils et techniques formelles offerts par la technologie synchrone. Nous illustrons particulièrement une analyse de synchronisabilité en utilisant les systèmes d'horloges affines. Des perspectives sont ensuite mentionnées concernant la modélisation d'applications hiérarchiques, et l'ajout d'automates de contrôle impliquant la vérification.

[22]

Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Algorithms and Tools for Parallel Computing On Heterogeneous Clusters, chapter Towards Distributed Process Networks with CORBA. Nova Science Publishers, Inc, 2006. ISBN: 1-60021-049-X.

[23]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Separating control and data flow: Methodology and automotive system case study. Research Report RR-5832, INRIA, France, January 2006.

[24]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Introducing control in the Gaspard2 data-parallel metamodel: Synchronous approach. Research Report RR-5794, INRIA, France, January 2006.

[25]

Abdelkader Amar, Pierre Boulet, and Philippe Dumont. Projection of the Array-OL specification language onto the Kahn process network computation model. In International Symposium on Parallel Architectures, Algorithms, and Networks, Las Vegas, Nevada, USA, December 2005.

The Array-OL specification model has been introduced to model systematic signal processing applications. This model is multidimensional and allows to express the full potential parallelism of an application: both task and data parallelism. The Array-OL language is an expression of data dependences and thus allows many execution orders.

In order to execute Array-OL applications on distributed architectures, we show here how to project such specification onto the Kahn process network model of computation. We show how Array-OL code transformations allow to choose a projection adapted to the target architecture.

[26]

Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, and Pierre Boulet. Towards UML 2 extensions for compact modeling of regular complex topologies - A partial answer to the MARTE RFP. In MoDELS/UML 2005, ACM/IEEE 8th International Conference on Model Driven Engineering Languages and Systems, pages 445–459, Montego Bay, Jamaica, October 2005. Lecture Notes in Computer Science vol. 3713.

The MARTE RFP (Modeling and Analysis of Real-Time and Embedded systems) was voted by OMG in February 2005. This request for proposals solicits submissions for a UML profile that adds capabilities for modeling Real Time and Embedded Systems (RTES), and for analyzing schedulability and performance properties of UML specifications. One of the particular request of this RFP concerns the definition of common high-level modeling constructs for factorizing repetitive structures, for software, hardware and allocation modeling of RTES. We propose an answer to this particular requirement, based on the introduction of multi-dimensional multiplicities and mechanisms for the description of regular connection patterns between model elements. This proposition is domain independent. We illustrate the use of these mechanisms in an intensive computation embedded system co-design methodology. We focus on what these factorization mechanisms can bring for each of the aspects of the co-design: application, hardware architecture, and allocation.

[27]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Introducing control in the Gaspard2 data-parallel metamodel: Synchronous approach. In International Workshop MARTES: Modeling and Analysis of Real-Time and Embedded Systems (in conjunction with 8th International Conference on Model Driven Engineering Languages and Systems), MoDELS/UML 2005, Montego Bay, Jamaica, October 2005.

In this paper, we study the introduction of control into the Gaspard2 application UML metamodel by using the principles of synchronous reactive systems. This allows to take the change of running mode into account in the case of data parallel applications, and to study more general ways of mixing control and data parallel processing. Our study is applied to a particular context using two different models, exclusively dedicated to the process of computation or control. The computation part represents the Gaspard2 application metamodels based on the Array-OL language which is often used to specify the data dependencies and the potential parallelism in intensive applications treating multidimensional data. The control part is represented by an automaton structure based on the mode-automata concept which makes it possible to clearly identify the different modes of a task and the switching conditions between modes.

The proposed UML metamodel makes it possible to describe the control automata, the different running modes and the link between control and computation parts. It also allows to clearly separate the control and data parts, and to respect the concurrency, the parallelism, the determinism and the compositionality of the Gaspard2 models.

[28]

Ashish Meena and Pierre Boulet. Model driven scheduling framework for multiprocessor SoC design. In Workshop on Scheduling for Parallel Computing (SPC 2005), Poznan, Poland, September 2005. ©Springer-Verlag.

The evolution of technologies is enabling the integration of complex platforms in a single chip, called a System-on-Chip (SoC). Mod- ern SoCs may include several CPU subsystems to execute software and sophisticated interconnect in addition to specific hardware subsystems. Designing such mixed hardware and software systems requires new me- thodologies and tools or to enhance old tools. These design to ols must be able to satisfy many relative trade-offs (real-time, performance, low power consumption, time to market, re-usability, cost, area, etc). It is recognized that the decisions taken for scheduling and mapping at a high level of abstraction have a major impact on the global design flow. They can help in satisfying different trade-offs before proceeding to lower level refinements.

To provide good potential to scheduling and mapping decisions we pro- pose in this paper a static scheduling framework for MpSoC design. We will show why it is necessary to and how to integrate different schedul- ing techniques in such a framework in order to compare and to combine them. This framework is integrated in a model driven approach in order to keep it open and extensible.

[29]

Lossan Bondé, Pierre Boulet, and Jean-Luc Dekeyser. Traceability and interoperability at different levels of abstraction in model transformations. In Forum on Specification and Design Languages, FDL'05, Lausanne, Switzerland, September 2005.

MDE (Model Driven Engineering) is a new approach of software design where the whole process of design and implementation is worked out around models. With MDE, a system is built by designing a set of models at different levels of abstraction. At the first level, only the main functionalities of the system are modeled. This first model is called according the MDA (Model Driven Architecture) terminology the PIM (Platform Independant Model). This PIM can be projected into one or more other models by transformations. These latter models being at lower levels of abstraction. When a model at a given level of abstraction integrates some platform (technology) information, it is called a PSM (Platform Specific Model). Model transformation is therefore a key issue of the MDE approach. However many questions arise about transformations. Among these questions is: When a model is transformed into different other models on different platforms, how to ensure the interoperability between these models?

This paper aims to provide an answer to the above question. Our approach is based on a traceability model. This model keeps links between the source and target model elements but also records the different operations that where performed in the transformation. We present a methodology for the automatic generation of the traceability model, and the exploitation of this model to ensure interoperability. An example based on OCP is provided to illustrate our proposal.

[30]

Lossan Bondé, Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet, Samy Meftaly, and Mickaël Samyn. Model Driven Engineering for Distributed Embedded Real-Time Systems, chapter Model Driven Architecture for Intensive Embedded Systems. ISTE, Hermes science and Lavoisier, August 2005. edited by Sébastien Gérard, Jean-Philippe Babeau and Joël Champeau.

[31]

Jean-Luc Dekeyser, Pierre Boulet, Philippe Marquet, and Samy Meftali. Model driven engineering for soc co-design. In NEWCAS'05, Québec, Québec, June 2005. IEEE.

[32]

Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, and Ashish Meena. Model driven engineering for regular MPSoC co-design. In ReCoSoC-05, Montpellier, France, June 2005.

The evolution of technologies is enabling the integration of complex platforms in a single chip, called a System-on- Chip (SoC).Modern SoCsmay include several CPU subsystems to execute software and sophisticated interconnect in addition to specific hardware subsystems. To manage and exploit this high degrees of provided parallelism in hw / sw, we need regular constructors both for hardware and software. SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the technology evolution, the best one is the one to come. Evolution of the embedded systems is not simple, both hardware and software, the business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of System on Chip we have to abstract from the technical concerns. Model Driven Engineering proposes a separation of concerns: application and technical concerns. Use of modeling standard can capitalize system descriptions and improve system evolution and integration.We propose the use of UML2 as a modeling language for MPSoC system design.

To model regular hardware and software, we propose to introduce multi-dimensional multiplicities and mechanisms for the description of regular connection patterns between model elements. This proposition is domain independent. We illustrate the use of these mechanisms in an intensive computation embedded system co-design methodology. We focus on what these factorization mechanisms can bring for each of the aspects of the co-design: application, hardware architecture, and allocation.

[33]

Jean-Luc Dekeyser, Philippe Marquet, Samy Meftali, Cédric Dumoulin, Pierre Boulet, and Smail Niar. Why to do without Model Driven Architecture in embedded system codesign?. In The first annual IEEE BENELUX/DSP Valley Signal Processing Symposium, (SPS-DARTS 2005), Antwerp, Belgium, April 2005.

The Model-Driven architecture is an initiative by the Object Management Group (OMG) to define an approach to software development based on modeling and automated mapping of models to implementations. The basic MDA pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs).

By defining different PIM and PSM dedicated to embedded systems, we will show the benefits of using the MDA approach in System on Chip codesign. From UML 2.0 profiles to System C or VHDL codes, the same model transformation engine is used with different rules expressed in XML.

[34]

Ouassila Labbani, Jean-Luc Dekeyser, and Pierre Boulet. Mode-automata based methodology for scade. In Springer, editor, Hybrid Systems: Computation and Control, 8th International Workshop, LNCS series, pages 386–401, Zurich, Switzerland, March 2005.

In this paper, we present a new design methodology for synchronous reactive systems, based on a clear separation between control and data flow parts. This methodology allows to facilitate the specification of different kinds of systems and to have a better readability. It also permits to separate the study of the different parts by using the most appropriate existing tools for each of them. Following this idea, we are particularly interested in the notion of running modes and in the Scade tool. Scade is a graphical development environment coupling data processing and state machines (modeled by the synchronous languages Lustre and Esterel). It can be used to specify, simulate, verify and generate C code. However, this tool does not follow any design methodology, which often makes difficult the understanding and the re-use of existing applications. We will show that it is also difficult to separate control and data flow parts using Scade. Regulation systems are better specified using mode-automata which allow adding an automaton structure to data flow specifications written in Lustre. When we observe the mode-structure of the mode-automaton, we clearly see where the modes differ and the conditions for changing modes. This makes it possible to better understand the behavior of the system. In this work, we try to combine the advantages of Scade and running modes, in order to develop a new design methodology which facilitates the study of several systems by respecting the separation between control and data flows. This schema is illustrated through the Climate case study suggested by Esterel Technologies, in order to exhibit the benefits of our approch compared to the one advocated in Scade.

[35]

Abdelkader Amar, Pierre Boulet, and Philippe Dumont. Projection of the Array-OL specification language onto the Kahn process network computation model. Research Report RR-5515, INRIA, March 2005.

The Array-OL specification model has been introduced to model systematic signal processing applications. This model is multidimensional and allows to express the full potential parallelism of an application: both task and data parallelism. The Array-OL language is an expression of data-dependences and thus allows many execution orders.In order to execute Array-OL applications on distributed architectures, we show here how to project such specification onto the Kahn process network model of computation. We show how Array-OL code transformations allow to choose a projection adapted to the target architecture. An experiment on a distributed process network implementation based on CORBA concludes this article.

Le modèle de spécification Array-OL a été créé pour décrire des applications de traitement du signal systématique. Il s'agit d'un modèle multidimensionnel permettant d'exprimer le parallélisme d'une application, que se soit le data parallélisme ou le parallélisme de tâche. De plus, Array-OL étant un langage d'expression de dépendances, il est possible d'avoir plusieurs ordres d'exécution. Afin de pouvoir exécuter Array-OL sur des architectures distribuées, nous proposons ici une projection d'Array-OL sur les réseaux de processus de Kahn en utilisant ces derniers comme modèles de calcul. Nous introduisons également des transformations qui permettent d'optimiser cette projection en fonction de l'architecture cible. Nous concluons en donnant un exemple basé sur une implémentation CORBA des réseaux de processus.

[36]

Philippe Dumont and Pierre Boulet. Another multidimensional synchronous dataflow: Simulating Array-OL in Ptolemy II. Research Report RR-5516, INRIA, March 2005.

Computation intensive multidimensional applications appear in many application domains such as video processing or detection systems. We present here the Array-OL specification model to handle such multidimensional applications. This model is compared to the Multidimensional Synchronous Dataflow proposition by Lee et al.We also detail in this a new domain in the Ptolemy simulation environment dedicated to Array-OL specification simulation.

Nous introduisons dans cet article le model de spécification Array-OL qui permet de gérer des applications à flots de données multidimensionels pour le traitement du signal. Nous comparons également Array-OL à Array-OL le seul modèle équivalent dans ce domaine. De plus nous proposons un nouveau « domaine » Ptolemy dédié à la simulation d'applications décrites en Array-OL.

[37]

Pierre Boulet and Ashish Meena. The case for globally irregular locally regular algorithm architecture adequation. In Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA'05), Dijon, France, January 2005.

In modern embedded systems, parallelism is a good way to reduce power consumption while respecting the real-time constraints. To achieve this, one needs to efficiently exploit the potential parallelism of the application and of the architecture. We propose in this paper a hybrid optimization method to improve the handling of repetitions in both the algorithm and the architecture. The approach is called Globally Irregular Locally Regular and consists in combining irregular heuristics and regular ones to take advantage of the strong points of both.

[38]

Arnaud Cuccuru, Pierre Boulet, and Jean-Luc Dekeyser. Regular hardware architecture modeling with UML2. In FDL04, Lille, France, September 2004.

[39]

Pierre Boulet, Jean-Luc Dekeyser, C̩dric Dumoulin, Philippe Marquet, Philippe Kajfasz, and Dominique Ragot. Sophocles: Cyber-enterprise for System-on-Chip distributed simulation РModel unification. In IFIP International Workshop on IP Based System-on-Chip Design, Grenoble, France, November 2003.

Complexity in the digital systems integration rises from the heterogeneity of the components integrated in a chip. The aim of the Sophocles project is to validate methodologies, platforms and technologies to support integration, verification and programming, over a distributed environment, of complex systems composed of heterogeneous virtual components. Several formalisms are gathered, according to their applicability, in order to immediately propose a framework of formal specification and validation of applications for SoCs. The unification of these formalisms in a modeling language facilitates the work of the users while guaranteeing a strong semantics on all the levels of the specification.

[40]

Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, and Philippe Marquet. MDA for SoC embedded design, intensive signal processing experiment. In SIVOES-MDA, San Francisco, USA, November 2003. Extended version of [DBDM03fdl].

[41]

Cédric Dumoulin, Pierre Boulet, Jean-Luc Dekeyser, and Philippe Marquet. MDA for SoC design, intensive signal processing experiment. In FDL'03, Frankfurt, Germany, September 2003. ECSI.

The development of embedded applications is very difficult. Several different languages are usually used to specify different parts of the application or of the hardware. Dealing with so many languages can be daunting. A separation of the preoccupations: application, hardware architecture, association between them and the simulation or execution technologies are keys to efficient co-design of embedded applications. The Model Driven Architecture can be used to better deal with the reuse of parts of the design and the interoperability between both the implementation technologies and the various simulation levels.

We propose a construction of metamodels to support a co-design methodology. This construction will be experimented on intensive signal processing application co-design to justify the adequacy of this methodology to usual industrial development techniques.

[42]

Cédric Dumoulin, Pierre Boulet, Jean-Luc Dekeyser, and Philippe Marquet. UML 2.0 structure diagram for intensive signal processing application specification. Research Report RR-4766, INRIA, March 2003.

Complexity in the digital systems integration rises from the heterogeneity of the components integrated in a chip. The simulation or code generation of such systems require to validate methodologies, platforms and technologies to support integration, verification and programming, of complex systems composed of heterogeneous virtual components. Several formalisms are needed according to their applicability in order to propose a framework of formal specification. The unification of these formalisms leads to visually model intensive signal processing applications for embedded systems. A part of this methodology has come down from the Array-OL language. An application is represented by a graph of dependences between tasks and arrays. Thanks to the data-parallel paradigm, a task may iterate the same code on different patterns which tile its depending arrays. The visual notation we propose uses a UML 2.0 standard proposal. This allows usage of existing UML 2.0 tools to model an application. A UML profile dedicated to Intensive Signal Processing with a strong semantics allows automatic code generation, automatic mapping on SoC architectures for early validation at the higher level of specification.

La complexité d'intégration des systèmes numériques vient de l'hétérogénéïté des composants intégrés sur une puce. La simulation ou la génération de code pour de tels systèmes nécessite la validation de méthodologies, de plate-formes et de technologies pour supporter l'intégration, la vérification et la programmation de systèmes complexes composés de composants virtuels hétérogènes. En fonction de leur domaine d'application, plusieurs formalismes sont nécessaires pour proposer un cadre de spécification formelle. L'unification de ces formalismes conduit à la modélisation visuelle d'applications de traitement de signal intensif pour systèmes embarqués. Une partie de cette méthodologie vient du langage Array-OL. Une application y est représentée comme un graphe de dépendances entre des tâches et des tableaux. En utilisant le paradigme du parallélisme de données, on peut décrire la répétition d'une même tâche sur différent motifs pavant les tableaux avec lesquels elle est en relation de dépendance. La notation visuelle que nous proposons utilise une proposition de standard UML 2.0. Nous pouvons ainsi réutiliser les outils UML 2.0 pour modéliser une application. Nous proposons ici un profil UML dédié au traitement de signal intensif avec une sémantique forte permettant la génération de code automatique ou le placement sur des architectures de type SoC pour une validation au plus tôt des spécifications.

[43]

Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser, and Frans Theeuwen. Distributed process networks using half FIFO queues in CORBA. Research Report RR-4765, INRIA, March 2003.

Process networks are networks of sequential processes connected by channels behaving like FIFO queues. These are used in signal and image processing applications that need to run in bounded memory for infinitely long periods of time dealing with possibly infinite streams of data. This paper is about a distributed implementation of this computation model. We present the implementation of a distributed process network by using distributed FIFOs to build the distributed application. The platform used to support this is the CORBA middleware.

Les réseaux de processus sont des processus séquentiels communicant uniquement par des canaux se comportant comme des files d'attentes. Ils sont utilisés pour modéliser des applications de traitement du signal ou de l'image devant fonctionner en mémoire bornée pendant des périodes de temps potentiellement infines et traitant des flux de donnés eux-aussi potentiellement infinis. Cet article s'intéresse à l'implémentation distribuée de ce modèle de calcul. Nous présentons l'implémentation distribuée de réseaux de processus grâce à l'utilisation de files d'attentes distribuées. La plate-forme logicielle utilisée est l'intergiciel CORBA.

[44]

Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Towards distributed process networks with CORBA. Scalable Computing: Practice and Experience, 5(4), December 2002.

[45]

Pierre Boulet, Jean-Luc Dekeyser, C̩dric Dumoulin, Philippe Kajfasz, Philippe Marquet, and Dominique Ragot. Sophocles: Cyber-enterprise for system-on-chip distributed simulation Рmodel unification. Research Report 02-06, Laboratoire d'Informatique Fondamentale de Lille, Universit̩ de Lille 1, France, June 2002.

Complexity in the digital systems integration rises from the heterogeneity of the components integrated in a chip. The aim of the Sophocles project is to validate methodologies, platforms and technologies to support integration, verification and programming, over a distributed environment, of complex systems composed of heterogeneous VCs. Several formalisms are gathered, according to their applicability, in order to immediately propose a framework of formal specification and validation of applications for SoCs. The unification of these formalisms in a modeling language facilitates the work of the users while guaranteeing a strong semantics on all the levels of the specification.

La complexité de l'intégration de systèmes numériques provient de l'hétérogénéïté des composants intégrés sur une puce. Le but du projet Sophocles est de valider des méthodologies, des plateformes et des technologies permettant le support de l'intégration, la vérfication et la programmation, dans un environnement distribué, de systèmes complexes composés de composants virtuels hétérogènes. Plusieurs formalismes sont regroupés selon leur domaine d'application dans le but de proposer immédiatement un cadre de spécification formelle et de validation d'applications sur systèmes sur silicium. L'unification de ces formalismes au sein d'un langage de modélisation facilite le travail des utilisateurs tout en garantissant une sémantique forte à tous les niveaux de la spécification.

[46]

Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Towards distributed process networks with CORBA. Research Report 02-04, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, May 2002.

Process networks is a widely used model to describe highly concurrent applications. We present here a distributed implementation of a slightly restricted process network model realized using the CORBA middleware. This implementation allows the non computer science specialist to easily program heterogeneous meta-applications based on an assembly of components communicating through FIFO queues.

Les réseaux de processus sont souvent utilisés pour décrire les applications fortement concurrentes. Nous présentons ici une implémentation distribuée d'une légère restriction de ce modèle utilisant l'intergiciel CORBA. Cette implémentation permet au non-informaticien de programmer facilement des méta-applications construites comme un assemblage de composants communicant via des files d'attentes.

[47]

Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Assembling dynamic components for metacomputing using CORBA. In Parallel Computing 2001, Naples, Italy, September 2001. Lecture Notes in Computer Science.

[48]

Pierre Boulet, Jean-Luc Dekeyser, Florent Devin, and Philippe Marquet. A visual development environment for meta-computing applications. In HCI International 2001, 9th Int'l Conf. on Human-Computer Interaction, New Orleans, LA, USA, August 2001. Lawrence Erlbaum Associates, Publishers.

Gaspard is a visual programming environment devoted to the development and control of scientific parallel applications.

The two paradigms of parallel programming (task and data parallelism) are mixed in Gaspard: a hierarchy of task graphs operates on array flows. These two levels are mixed in a common metaphor. An application is designed as a printed circuit: the programmer specifies tasks as boards or chips and instantiates tasks by plugging them into slots.

The number crunching applications developped using Gaspard are deployed on metacomputing platforms. The visual specification of the application mapping may be dynamically modified at runtime according to the information provided by Gaspard.

[49]

Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, and Alain Demeure. Visual data-parallel programming for signal processing applications. In 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, pages 105–112, Mantova, Italy, February 2001.

Matrix manipulation programs are easily developed using a visual language. For signal processing, a graph of tasks operates on arrays. Each task iterates the same code on different patterns tilling these arrays. In this case visual specifications of dependencies between the pattern elements are enough to define an application. From the Array-OL language developed by Thomson Marconi Sonar, we propose a graphical environment, Gaspard, dedicated to the data-parallel paradigm. Only elementary SPMD tasks are textual. A full environment has been implemented including the graphical editor, a code transformer and a code generator for SMP computers.

[50]

Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, François Piriou, Pierre Boulet, and Stéphane Clenet. High level parallelization of a 3D electromagnetic simulation code with irregular communication patterns. In 4th International Meeting on Vector and Parallel Processing (VECPAR'2000), pages 519–528, Porto, Portugal, June 2000. Lecture Notes in Computer Science vol. 1470.

[51]

Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, François Piriou, Pierre Boulet, and Georges Marques. Parallelization of 3D magnetostatic code using High Performance Fortran. In International Conference on Parallel Computing in Electrical Engineering, PARELEC'2000, pages 181–185, Trois-Rivières, Quebec, Canada, August 2000.

[52]

Emmanuel Cagniot, Jean-Luc Dekeyser, Pierre Boulet, Thomas Brandes, François Piriou, and Georges Marques. Parallélisation d'un code 3D magnétostatique avec le langage de programmation High Performance Fortran. In Conférence Européenne sur les Méthodes Numériques en Éléctomagnétisme, NUMELEC'2000 (poster session), pages 184–185, Poitiers, France, March 2000. (In French).

[53]

Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, and Alain Demeure. Visual data-parallel programming for signal processing applications. Research Report 00-05, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, February 2000.

Matrix manipulation programs are easily developed using a visual language. For signal processing, a graph of tasks operates on arrays. Each task iterates the same code on different patterns tilling these arrays. In this case visual specifications of dependencies between the pattern elements are enough to define an application. From the Array-OL language developed by Thomson Marconi Sonar, we propose a graphical environment, Gaspard, dedicated to the data-parallel paradigm. Only elementary SPMD tasks are textual. A full environment has been implemented including the graphical editor, a code transformer and a code generator for SMP computers.

[54]

Pierre Boulet and Xavier Redon. SPPoC : fonctionnement et applications. Research Report 00-04, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, February 2000.

The polyhedral model is quite popular in the field of parallel computing. So, research prototypes tend to use tools like PIP (parametric integer programming solver), the PolyLib (library for polyhedra manipulation) or Omega (library and calculator for Presburger formulas). The two main drawbacks of these tools are a poor human-computer interface and a lack of agressive simplification. This last deficiency leads to sequences of computations which give too complex results or even that cannot be completed due to memory exhaustion or time constraints. The SPPoC calculator brings a solution to these problems due to its interactive and totally symbolic interface and to its advanced simplification modules. It allows also the unification of different tools. We present two applications which use SPPoC: a code generator and a communication volume estimator

Dans le domaine de l'informatique parallèle, le modèle polyèdrique est très souvent utilisé. Les prototypes de recherche dans ce domaine utilisent donc souvent des outils comme PIP (résolution paramétrique de programes linéaires), la PolyLib (bibliothèque de manipulation de polyèdres) ou Omega (bibliothèque et interface de manipulation de formules de Presburger). Les deux principaux problèmes de ces outils sont leur manque de convivialité et des modules de simplification trop primitifs. Le manque de simplification fait que l'enchaînement de calculs conduit à des résultats incompréhensibles ou qui n'aboutissent pas pour des problèmes de mémoire ou de temps. La calculatrice SPPoC résoud ces problèmes grâce à son interface interactive totalement symbolique et à des modules de simplification des résultats plus poussés. Elle permet aussi d'unifier différents outils. La présentation de SPPoC est illustrée par deux applications : une application de génération de code et une application d'estimation de volume de communications

[55]

Pierre Boulet and Xavier Redon. SPPoC: Symbolic parameterized polyhedral calculator. In Workshop Compilation et Parallélisation Automatique, St Nabor, France, October 1999. (In French). Slides of the presentation.

[56]

Pierre Boulet, Jean-Luc Dekeyser, Alain Demeure, Florent Devin, and Philippe Marquet. Une approche à la SQL du traitement de données intensif dans Gaspard. In RenPar'11, Rencontres Francophones du Parallélisme des Architectures et des Systèmes, Rennes, France, June 1999. (In French).

The Gaspard (Graphical Array Specification for PARallel and Distributed computing) project is a visual specification environment for data-parallelism. We describe here the specification model used in Gaspard. This model inherits from the Array-OL one. We then define an SQL inspired approach to intensive data treatment that proposes a language to describe irregular components.

Le projet Gaspard (Graphical Array Specification for PARallel and Distributed computing) est un environnement de spécification visuelle pour le data-parallélisme. Nous décrivons le modèle de spécification utilisé dans Gaspard défini comme extension du modèle Array-OL. Nous définissons ici une approche du traitement de données intensif inspiré de SQL qui propose un langage de description de composants irréguliers.

[57]

Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, François Piriou, Pierre Boulet, Stéphane Clénet, Yvonnick Le Menach, and Georges Marques. Parallelization of a Fortran 90 program for electromagnetic problems. In 3rd Annual HPF User Group Meeting, HUG'99, Redondo Beach, CA, USA, August 1999.

[58]

Pierre Boulet and Xavier Redon. Communication pre-evaluation in HPF. In Euro-Par'98, pages 263–272. Lecture Notes in Computer Science vol. 1470, 1998.

Parallel computers are difficult to program efficiently. We believe that a good way to help programmers write efficient programs is to provide them with tools that show them how their programs behave on a parallel computer. Data distribution is the major performance factor of data-parallel programs and so automatic data layout for HPF programs has been studied by many researchers recently. The communication volume induced by a data distribution is a good estimator of the efficiency of this data distribution. We present here a symbolic method to compute the communication volume generated by a given data distribution during the program writing phase (before compilation). We stay machine-independent to assure portability. Our goal is to help the programmer understand the data movements its program generates and thus find a good data distribution. Our method is based on parametric polyhedral computations. It can be applied to a large class of regular codes.

[59]

Vincent Bouchitte, Pierre Boulet, Alain Darte, and Yves Robert. Evaluating array expressions on massively parallel machines with communication/computation overlap. International Journal of Supercomputer Applications and High Performance Computing, 9(3):205–219, 1995.

[60]

Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Evaluating array expressions on massively parallel machines with communication/computation overlap. In B. Buchberger and J. Volkert, editors, Parallel Processing: CONPAR 94-VAPP VI, volume 854 of LNCS, pages 713–724. Springer Verlag, 1994. Extended version available as TR94-10, LIP, ENS Lyon.

[61]

Pierre Boulet. Outils pour la parallélisation automatique. PhD thesis, École normale supérieure de Lyon, January 1996.

[62]

Pierre Boulet. Bouclettes: A fortran loop parallelizer. In HPCN 96, pages 784–791, Bruxelles, Belgium, June 1996. Springer Verlag Lecture Notes in Computer Science.

[63]

Pierre Boulet and Thomas Brandes. Evaluation of automatic parallelization strategies for hpf compilers. In HPCN 96, pages 778–783, Bruxelles, Belgium, June 1996. Springer Verlag Lecture Notes in Computer Science.

[64]

Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-ultimate tiling ? In IEEE Computer Society Press, editor, Scalable High Performance Computing Conference, pages 568–576, 1994. Extended version available as Technical Report 93-36, LIP, ENS Lyon (1993).

[65]

Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (pen)-ultimate tiling? Integration, the VLSI Journal, 17:33–51, 1994.

[66]

Pierre Boulet, Alain Darte, Georges-André Silber, and Frédéric Vivien. Loop parallelization algorithms: from parallelism extraction to code generation. Technical Report 97-17, LIP, ENS-Lyon, France, June 1997.

[67]

Pierre Boulet, Alain Darte, Georges-André Silber, and Frédéric Vivien. Loop parallelization algorithms: From parallelism extraction to code generation. Parallel Computing, 24(3-4):421–444, May 1998.

[68]

Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (pen)-ultimate tiling? Integration, the VLSI Journal, 17:33–51, 1994.

[69]

Pierre Boulet, Jean-Luc Dekeyser, Alain Demeure, Florent Devin, and Philippe Marquet. Une approche à la SQL du traitement de données intensif dans textsc Gaspard. In Renpar'11, 1999.

[70]

Pierre Boulet and Michèle Dion. Code generation in Bouclettes. Technical report, Laboratoire de l'Informatique du ParallÈlisme, 1995.

[71]

Pierre Boulet and Michèle Dion. Code generation in Bouclettes. In Proceedings of the Fifth Euromicro Workshop on Parallel and Distributed Processing, pages 273–280, London, UK, January 1997. IEEE Computer Society Press.

[72]

Pierre Boulet, Michèle Dion, Eric Lequiniou, and Tanguy Risset. Reference manual of the bouclettes parallelizer. Research Report 94-04, Laboratoire de l'Informatique du Parallélisme, October 1994.

[73]

Pierre Boulet, Jack J. Dongarra, Fabrice Rastello, Yves Robert, and Frédéric Vivien. Algorithmic issues on heterogeneous computing platforms. Parallel Processing Letters, 9(2):197–213, 1999.

[74]

Pierre Boulet, Jack J. Dongarra, Yves Robert, and Frédéric Vivien. Tiling for heterogeneous computing platforms. Technical Report UT-CS-97-373, University of Tenessee, 1997.

[75]

Pierre Boulet, Jack J. Dongarra, Yves Robert, and Frédéric Vivien. Static tiling for heterogeneous computing platforms. Parallel Computing, 25(5):547–568, may 1999.

[76]

Pierre Boulet and Paul Feautrier. Scanning polyhedra without DO-loops. In PACT'98, pages 4–11. IEEE Computer Society, 1998.

[77]

Pierre Boulet and Paul Feautrier. Scanning polyhedra without do-loops. Technical report, Laboratoire PRiSM, Université de Versailles-St Quentin en Yvelines, France, 1998. available at url http://www.lifl.fr/ boulet/publi/polyscanRR.ps.gz.

[78]

Pierre Boulet and José A.B. Fortes. Experimental evaluation of affine schedules for matrix multiplication on the maspar architecture. In Proceedings MPCS'94, pages 452–459, 1994.

[79]

Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (pen)-ultimate tiling? in "shpcc 94". In J.J. Dongarra and D. Walker eds, editors, IEEE Computer Society Press, pages 568–576, 1994.

[80]

Pierre Boulet and Xavier Redon. Communication pre-evaluation in HPF. In EUROPAR'98, volume 1470 of LNCS, pages 263–272. Springer Verlag, 1998.

[81]

Vincent Bouchitté, Pierre Boulet, Alain Darte, and Yves Robert. Evaluating array expressions on massively parallel machines with communication/computation overlap. Technical Report 94-10, Laboratoire de l'Informatique du Parallélisme, ENS Lyon, March 1994.

[82]

Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-ultimate tiling ? Technical Report 93-36, Laboratoire de l'Informatique du Parallélisme, Ecole Normale Supérieure de Lyon, November 1993.

[83]

Pierre Boulet, Alain Darte, Tanguy Risset, and Yves Robert. (Pen)-ultimate tiling ? In IEEE Computer Society Press, editor, Scalable High Performance Computing Conference, pages 568–576, 1994. Extended version available as Technical Report 93-36, LIP, ENS Lyon (1993).